1. Field of the Invention
The present invention relates to a driver circuit and driver cell for a display device.
2. Description of the Related Art
A driver circuit for a display device is generally formed as an integrated circuit chip. The chip is sometimes referred to as a source driver because it is connected to the source terminals of transistors in the display panel of the display device.
FIG. 1 shows a conventional source driver chip 10. The chip includes logic circuits 11, level shifters 13, decoders 13, operational amplifiers (OP-AMPs) 14, output pads 15, and one or more ladders 18 formed on a rectangular chip substrate 16. Responsive to input of an image data signal, the logic circuits 11, level shifters 13, decoders 13, and operational amplifiers 14 select voltages generated by the ladders 18 to generate voltage signals representing the gradation levels of pixels in the image.
The logic circuits 11, level shifters 13, decoders 13, and operational amplifiers 14 are conventionally laid out in the order shown, with the logic circuits 11 near one long side 16A of the chip substrate 16 and the operational amplifiers 14 near the opposite long side 16B. The output pads 15 are formed on both long sides 16A, 16B of the substrate. Descriptions of driver circuits of this type can be found in, for example, Japanese Patent Application Publications No. 2009-59957 and 2009-253374.
FIG. 2 shows an enlarged view of a conventional driver circuit, showing the part encircled by the dotted line X in FIG. 1. There is one logic circuit 11, one level shifter 12, one decoder 13, one operational amplifier 14, and one output pad 15 for each column of pixels in the display panel. That is, there is one output signal channel for each column of pixels. The logic circuit 11, level shifter 12, decoder 13, and operational amplifier 14 for one channel constitute a driver cell. The arrows in FIG. 2 indicate the flow of input data through the driver cells.
The driver cells for two channels are normally formed as a single circuit group. FIG. 2 shows two such circuit groups A and B. The output pads 15 of adjacent circuit groups are disposed on opposite sides of the chip substrate 16. In FIG. 2 the output pads 15 of circuit group A are on side 16A and the output pads 15 of circuit group B are on side 16B.
The operational amplifiers 14 are connected to the output pads 15 by metal wiring patterns 17A, 17B. Metal wiring patterns 17B extend from the operational amplifiers 14 in circuit group B to output pads 15 on the adjacent side 16B, but metal wiring patterns 17A must make lengthy detours around circuits 11-14 to reach the output pads 15 on the opposite side 16A.
A problem with the arrangement shown in FIG. 2 is that since the length of the metal wiring patterns connecting the operational amplifiers to the output pads differs from channel to channel, the output characteristics of the channels are non-uniform. A particular problem is that the wiring resistance in the long metal wiring patterns 17A adversely affects the slew rate of the signals output from circuit group A.